1. Field of the Invention
The present invention is directed to a metal-to-metal antifuse structure for use in microcircuit structures such as Field Programmable Gate Arrays (FPGAs) and the like. More particularly, the antifuse structure of the present invention comprises an antifuse cell opening in which is deposited a barrier metal over which is deposited the antifuse material layer and then another barrier metal layer. In this way the capacitance of the antifuse is reduced resulting in a device compatible with higher operating speeds.
2. The Prior Art
Prior art metal-to-metal antifuse structures generally comprise a planar bottom electrode on top of which is disposed a planar barrier metal layer. An interlayer dielectric layer (ILD) is disposed over the bottom electrode structure and an antifuse cell opening is formed in the ILD to expose the bottom electrode. An antifuse material layer may then be deposited in the antifuse cell opening (or "via") and appropriate layers deposited over the antifuse material layer. The problem with this approach is that it requires a thicker barrier layer on top of the bottom electrode which is not a standard process in CMOS backend technology. For manufacturability, it is desirable to have antifuse related processes impose as little change as possible on the process technology.